1. Field of the Invention
This invention relates to an echo canceller based on a prescribed echo model.
2. Description of Related Art
In general receiver terminal devices, an audio signal from an exchange network is introduced via a four-line circuit, and this is supplied to many types of service by a two-line circuit. At the termination of such a communication circuit, various echo cancelling techniques are used in order to deal with impedance mismatching. These techniques are disclosed in the reference “Introduction to Adaptive Filters”, S. Haykin, Macmillan Publishing Co., New York, and elsewhere.
For example, there is a technique which uses an echo canceller with the configuration shown in the block diagram of FIG. 2. In FIG. 2, this echo canceller 10 which is an example of the conventional art has a receiving signal route comprising a reception input terminal Rin 11 for reception from the exchange network, an analog/digital converter 12, an input reference point 13 for an adaptive filter 40, described below, a digital/analog converter 14, and a reception output terminal Rout 19.
Signal exchange from a four-line circuit network to a two-line circuit via a hybrid transformer 20 is performed, and a transmission signal route comprises a transmission input terminal Sin 31, another analog/digital converter 32, a pseudo-code signal Y(n) adder 33, a residual echo difference (residue) signal e(n) output detection point 34, another digital/analog converter 35, a transmission output terminal Sout 39, and an adaptive filter 40 having a prescribed adaptive algorithm.
In this echo canceller 10, an audio signal X from a remote location is input to the reception input terminal Rin 11 via an exchange network, not shown, and is converted into a digital reception signal X(n) by an analog/digital converter 12. When this reception signal X(n) passes through the input reference point 13, it is again converted into an analog signal by the digital/analog converter 14, and is input to the hybrid transformer 20. The analog signal is led to a receiving terminal device via a two-line circuit, not shown. Here the lowercase letter “n” signifies that the audio signal X is sampled at time n to result in the nth signal.
At this time, at the hybrid transformer 20, part of the analog symbol becomes an echo signal y due to inevitable impedance mismatching, and is reflected to the transmission input terminal Sin 31. When this echo signal y is converted into a digital signal y(n) by the analog/digital converter 32, the digital signal is canceled by the pseudo-echo signal Y(n) of the adaptive filter 40 through the adder 8. However, the when residue signal e(n) is input to the digital/analog converter 35 via the output detection point 34, it is again converted into an analog signal and transmitted from the transmission output terminal Sout 39 to the remote transmission terminal device.
Hence at the adaptive filter 40, the pseudo-echo signal Y(n) is controlled such that this residue signal e(n) is minimized. That is, digital signal processing is performed while monitoring the reception signal X(n) at the input reference point 13, and in addition the pseudo-echo signal Y(n) is formed based on the residue signal e(n) from the output detection point 34. By means of such an echo canceller 10, the echo signal y returned to the remote transmission terminal device can be eliminated to the maximum extent, and the voice communication quality of the exchange network can be improved, so that such echo cancellers are widely used. From the reception terminal device, the transmission signal is sent to the exchange network independently of the echo signal y, via the hybrid transformer 20, this echo canceller 10, and the transmission output terminal Sout 39.
Next, an example of the functions of the adaptive filter 40 is shown in the block diagram of FIG. 3, and an example of the technique for generating a specific pseudo-echo signal Y(n) is explained. This adaptive filter 40 comprises a cyclic FIR filter portion 41, which is a well-known FIR (finite impulse response) filter, and a coefficient update portion 50 to update the filter coefficient (tap coefficient).
The FIR filter portion 41 comprises a variable register 42 for the reception signal X(n) train, a multiplier-accumulator 43 to perform multiplication and accumulation according to the respective delays, and a coefficient register 44 for the tap coefficient. The coefficient update portion 50 has delay taps 51 for the reception signal X(n) train, a power calculation portion 52 for each reception signal X(n), a divider 53 using the power signal, and an update amount calculation portion 54 for each tap coefficient based on the residue signal e(n) for each reception signal X(n).
By this means, the tap coefficient is updated according to the power of the reception signal X(n) train by the update amount calculation portion 54, for reception signals X(n) which cause residue signals e(n). The multiplier-accumulator 43 of the FIR filter portion 41 can then generate a pseudo-echo signal Y(n) for each reception signal X(n) while changing the tap coefficient from one moment to the next. For example, using a digital signal processor (DSP) system, the complicated functions of each portion can be realized through publicly-known digital signal processing techniques. In this case, a simple configuration is adopted for the delay taps 51, which also serve as the variable register 42. Below, the respective processing stages are briefly explained.
The train of reception signals X(n) is input to the FIR filter portion 41 and coefficient update portion 50. In the FIR filter portion 41, these are sequentially guided into the variable register 42, as shown in FIG. 4A, to become a train of delay sample signals at time n (in the figure, from X(0) to X(N−1)). As a result, a pseudo-echo signal Y(n) is generated by the multiplier-accumulator 43 using the following equation (1). N−1 memory cells are provided in the variable register 42, and x(0) is directly multiplied.Y(n)=ΣX(n−k)×Hk(n)  (1) 
That is, when the product of the train of delay sample signals X(n) of the variable register 42 and the tap coefficients Hk(n) is accumulated over the range k=0 to N−1, the multiply-accumulate sum can be taken as the pseudo-echo signal Y(n).
Hence by updating the tap coefficients Hk(n) of the coefficient register 44 from moment to moment while monitoring the power of the reception signal X(n), an adaptive filter 40 for the echo path can be configured. Hence in the coefficient update portion 50, the following equation (2) is used by the power calculation portion 52 to calculate the power signal POWER(n).POWER(n)=Σ(X(n−i)×X(n−i))  (2) 
That is, each time a new delay sample signal X(n) is input, multiply-accumulate is performed over the range i=0 to N−1, as shown in the time chart of FIG. 4B, and the result taken to be the reception signal power. As with the variable register 42, the delay taps 51 are provided with N−1 memory cells.
Next, in the divider 53, the reciprocal IAEP1 of the power signal POWER(n) is calculated for each delay sample signal X(n) using the following equation (3). Here the constant α is taken to be a constant value which determines the speed of convergence of the echo canceling function, and is in the range 0<α<1.IAEP1=(α/POWER(n))  (3) 
In the update amount calculation portion 54, the calculated result of this equation (3) is substituted into the following equation (4) to calculate the tap coefficients Hk(n) of the FIR filter 41.Hk(n+1)=Hk(n)+IAEP1×e(n)×X(n−i)  (4) 
The method of equation (3) is widely known as the NLMS (normalized LMS) method. By means of this NLMS method, update amounts for tap coefficients Hk(n) can be calculated for each delay sample signal X(n), and so a pseudo-echo signal Y(n) can be determined while causing the adaptive filter 40 to adapt closely to the transmission characteristics of the echo path.
However, in the above echo canceller example of the prior art, the tap coefficients Hk(n) are calculated using equations (3) and (4), and so the following problems arise from the large amount of calculations.
In general DSPs, although the amount of processing (number of operations) in multiply-accumulate processing is small, division requires several times the processing of multiplication and accumulation. Moreover, in division equations often limits are placed (regarding range, sign, and so on) on the numerator or denominator, and in such cases division preprocessing must be performed, and measures taken to ensure that the numerator and denominator are within limits which depend on each DSP. Because this preprocessing is also executed by the DSP as part of the division operation, there is the problem that even a single division operation can impose an extremely large burden on the DSP.
A device such as an echo canceller which performs signal processing for such for example as audio communication must execute realtime processing of signals occurring in realtime. Hence a DSP must complete all necessary signal processing within the allowed time range and within the allowed calculation amounts. However, if division is performed each time a delay sample is introduced, a large part of the allowed calculation amount will be consumed by division operations. Hence there is the problem that a large calculation capacity cannot be left for the above-described vital multiply-accumulate operations.
Consequently, an echo canceller is desired which can rationally resolve these problems, and reduce the amount of power signal division calculations, when calculating the update amounts of tap coefficients in an adaptive filter.